Welcome to the official portal for the CSP4CMSIS ecosystem. Based in Cambridge, this project focuses on the implementation of Communicating Sequential Processes (CSP) for ARM-based embedded systems, providing a mathematically sound foundation for high-integrity AI deployment.
In the era of “AI at the Edge,” the industry faces a Safety Wall. Traditional “Super-loop” architectures cannot guarantee the deterministic behavior required for safety-critical systems when integrated with non-deterministic AI inference.
CSP4CMSIS solves this by providing a zero-heap, static-memory mapping of CSP primitives directly onto ARM CMSIS-RTOS and FreeRTOS.
We leverage the power of process algebra to model system behavior:
Access the core technical resources for designing safe process networks:
Explore our implementation across the ARM ecosystem:
| Target Hardware | Complexity | Repository Link |
|---|---|---|
| Nucleo-F401RE | Entry Level | View Repo |
| Nucleo-G474RE | Intermediate | View Repo |
| Cortex M55 / Ethos NPU | Flagship / AI | View Repo |
| DISCO-L475VG-IOT01A (B-L475E-IOT01A) | Intermediate | View Repo |
We are currently seeking partners for the DSIT TechLocal AI Professional Degree and Traineeship Accelerator.
The Objective: To develop a Level 7 (Masters equivalent) curriculum focused on “Certifiable AI.” We aim to provide graduates with the skills to deploy AI on ARM Ethos NPUs using formally verified process networks.
Calling ARM & Cambridge-based Industry Partners: If you are interested in supporting this traineeship model or integrating these formal methods into your safety-critical workflow, please get in touch.